Description
Syntronic China R&D Center is looking for SOC UVM Engineer.
Responsibilities
> Proficient of System Verilog program capability.
> Experience on Python/Perl/Makefile script.
> Experience on C/C++ or more SystemC modeling languages.
> Experience on UVM project time plan、environment construction、Test case generation and coverage analysis.
> Experience on the CHI protocol, CXL and PCIE6-FLIT, and low-power related verification is preferred
> Experience on One or more of the AMBA ACE、PCIE、DDR、MAC/PHY Verification related is preferred
Requirements
> Bachelor’s or master’s degree of communication, Computer Science, Electrical Engineering or related is preferred. >3 Years experience.
> Product development knowledge and Product Lifecycle Management knowledge.
> Basic English, both spoken and written.
> Excellent communication skills.