岗位职责:

1. Work closely with process RD team to develop DRC/LVS for design readiness.
2. Provide customer support to world-wide leading design house.
3. Initial more innovation to continue optimize development efficiency.
4. Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
5. Work closely with EDA partner for tool qualification and methodology enhance.

1. Good knowledge of semiconductor FEOL/BEOL process and chip design
2. Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
3. Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
4. Ability to work across teams to drive a solution, problem solver and self-motivated.
5. The ideal candidate will have experience in DRC/LVS development.
6. MS or above in EE, CS related fields.